ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools

• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems

• Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage

• Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals

• Run and debug non-timing and SDF annotated gate level simulations

• Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation

• Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science

• 1+ years of professional experience working with ASICs

• Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:

• Understanding of ASIC design flow, methodologies, physical design, and verification

• Experience with high reliability design and implementations

• Good scripting skills (csh/bash, Perl, Python etc.)

• Familiar with implementation or integration of design blocks using