PB
PBridge

NPU Architect

semronDresden, United StatesPosted 30+ days ago

About the role

In this role you'll be responsible to design the next iteration of SEMRON's 3D in-memory compute chip. You will collaborate with a team of hardware, compiler and ML engineers to optimise all aspects of executing ML workloads based on our capacitive analog in-memory matrix-vector multiplication units. Design and specify…

Full details and requirements are on the company's own posting.

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