Verification Designer

Fidus is a global high-tech design firm headquartered in Ottawa, with additional design centres in Kitchener-Waterloo and San Jose. We specialize in leading-edge electronic product development, with hardware, embedded software, FPGA/ASIC, and signal integrity teams working together to design and deliver next-generation products for clients in emerging technology markets.

Position Overview/Mandate

The Verification Designer owns block- and system-level verification of ASIC and FPGA designs for Fidus clients, planning and executing complex verification projects end to end — building UVM, formal, and assertion-based verification environments and driving coverage closure.

This role is ideal for someone who takes lead-level ownership of verification strategy, is comfortable moving between different application domains (communications, storage, signal processing, video), and takes pride in producing thorough, well-documented verification work — often working directly with clients on verification approach.

Make an Impact with US

At Fidus, you'll work on high-speed, high-complexity electronic systems, often using emerging technologies before they reach the broader market. You'll collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout, and mechanical/thermal design as part of cross-functional teams delivering real products for our clients.

In practice, that means contributing to projects in areas such as space and satellite systems, next-generation communications and networking, high-performance compute and storage platforms, advanced video, imaging, VR/AR applications, and industrial, medical, and automotive systems. You won't be limited to a single product or industry—your work will follow the technology, not just one roadmap.

What You'll Be Doing

• Own block- and system-level verification of ASIC and FPGA designs, from test plan development through coverage closure.

• Design and implement UVM, formal, and assertion-based verification environments, applying constrained-random verification (CRV) techniques.

• Develop behavioral models and write test cases to achieve functional coverage goals; define and track coverage metrics to closure.

• Debug and troubleshoot failures in simulation and regression runs, collaborating with designers and system architects to resolve issues.

• Automate verification tasks and monitor regressions using scripting (Python, Perl, or Tcl).

• Plan, execute, and report status on multiple verification activities as a verification lead.

• Work directly with external clients on verification strategy and support.

Who You are

• 8+ years of ASIC/FPGA verification experience, with proven verification-lead ownership — able to plan and execute complex verification projects end to end.

• Strong SystemVerilog and UVM methodology fluency, including constrained-random verification (CRV) techniques.

• Experience with functional coverage, assertions, and formal verification techniques; comfortable defining and tracking coverage metrics to closure.

• Familiarity with industry-standard protocols such as Ethernet, DDR/LPDDR, HBM, security, networking, AXI, NoC, and ARM CPU subsystems.

• Experience with alternative verification environments (cocoTB, pyUVM, DPI-C) is a plus.

• Proficiency in scripting languages (Python, Perl, or Tcl) to automate verification tasks.

• Strong debugging skills, problem-solving ability, and analytical thinking.

• Strong interpersonal, teamwork, and communication skills; comfortable being client-facing.

• Embraces AI as part of a modern engineering toolkit.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Location and travel: Fully remote role and travel may be required domestically and internationally to support customer engagements and project delivery.

Benefits

Our competitive compensation package also includes a comprehensive benefits package, including medical, dental, and