Manager, ASIC Design Engineering (Starshield Silicon)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

MANAGER, ASIC DESIGN ENGINEERING (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads.

The Manager, ASIC Design Engineering will lead a team that develops ASICs and FPGAs for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. From initial design through on-orbit operations this lead is responsible for leading a phenomenal team of engineers in a collaborative effort to design, manufacture, test and operate chips for satellites that make our Nation safer.

RESPONSIBILITIES:

• Lead a small team responsible for the digital design of ASICs and/or FPGAs for Starshield projects.

• Lead architectural trades for features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.

• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.

• Work closely with verification team to ensure all aspects of the design are covered and verified.

• Work with leaders across the engineering organization to drive product requirements to push the performance envelope for Starshield satellites.

• Recruit, develop, train, and retain world class team members who will deliver for our Nation and amplify the team.

• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).

• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, computer science, or another engineering discipline.

• 5+ years of experience in RTL implementation and/or FPGA/ASIC development.

• 2+ years of experience with direct report management or mentoring an engineering team.

PREFERRED SKILLS AND EXPERIENCE:

• Experience solving problems including clock domain crossings and power optimization.

• Experience developing complex ASICs.

• Experience with multicore CPU subsystem design.

• Experience with standard bus protocols (e.g. AXI, AHB, etc.).

• Experience with embedded processors.

• Experience with high speed and low power design techniques.

• Scripting skills